Lift-off is a subtractive process used in wafer fabrication of Micro-Electrical-Mechanical-Systems (MEMS) devices to pattern deposited films, often metal, that are challenging to dry etch. To achieve a successful lift-off, the lift-off process begins by depositing and then patterning a photoresist masking material onto a silicon wafer using photolithographic techniques. An important characteristic of the photoresist is undercutting the resist sidewalls after developing, protecting them from being coated with metal during deposition. After deposition, the photoresist and metal layer is removed via solvent. The purpose of our research is to allow for a more varied range of fabrication using positive tone photoresist. Negative tone photoresist is typically used for this lift-off process because after development, this resist naturally forms the desired undercut. Alternately, positive tone photoresist is characterized by a tapered sidewall that is difficult to not coat with the metal film layer, making the removal step via solvent problematic. We hypothesized an advantageous undercut is possible with positive tone photoresist using a white light diffuser that would allow light to enter at angles through our mask during the exposure step. We evaluated resist undercut using the Nikon microscope and resist/metal sidewall characteristics using the Scanning Electron Microscope. We will assess the new resist exposure technique using both line-of-sight evaporation (physical vapor deposition in which a target material’s atoms precipitate into solid form, when heated up under high vacuum, coating everything in the vacuum chamber) and sputtering (metal deposition involving particle ejection of ions) to deposit a thin metal film. We anticipate evaporated metal to lift-off easily with the new technique, which indicates a crowning demonstration of success.

Photoresist is a viscous light sensitive organic solution which is used to coat the surface of silicon substrates in nanofabrication processes. An essential step in nanofabrication is photolithography. During this procedure, photoresist is deposited in a uniform, thin film over the wafer surface using a tool called the Spin Coater.  The purpose of our experiment is to develop spin curves that will examine the correlation between the different speeds or RPM value that the wafer is spun at and the uniformity of the photoresist coated wafer. The thickness and uniformity are critical to determine the correct UV exposure dose and plasma etch times. We will analyze the results for both positive and negative photoresist. In the case of a positive photoresist, the regions that are exposed to light are dissolved in developer. On the other hand, with negative photoresist, regions that were not exposed to light are dissolved. After the wafers are spun, the uniformities will be measured by an automated thickness mapping system called Filmetrics. Filmetrics is a machine that allows for the surface to be measured at the nano-meter level. The spin curves experiment will allow researchers to obtain wafers using these photoresists to achieve photolithography with their desired thickness.

The damascene process is an additive manufacturing technique commonly used in the nanofabrication industry to produce semiconductor devices. This process utilizes deposition and patterning of successive layers to produce interconnected copper patterns separated by interlayer dielectric. The goal of this project was to implement the damascene process to develop and refine methods at the Washington Nanofabrication Facility (WNF) for manufacturing multi-layer devices. For our purposes, we constructed an integrated passive device (IPD) that contains capacitors, resistors, and inductors. We utilized basic nanofabrication tools in our damascene process including deposition, photolithography, etching, electroplating, metrology, and polishing tools. In fabricating this method at the WNF, our main objective was to produce a highly repeatable device with structural integrity. The main challenges accompanied with this involved generating a successful etch on all three layers of the IPD and optimizing polishing conditions. Cross sections of the final product were analyzed in order to demonstrate that the layout expected from the process was achieved. The procedure we developed can be applied to future multi-layer damascene processes at the WNF. Multi-layer devices are significant in the semiconductor industry as they allow for high packing density and an increased variety of circuit configurations in a compact device.

Atomic Layer Deposition (ALD) is a process whereby thin films of a material, ranging from dielectric materials to metals, are deposited onto a substrate. ALD reactions operate using two vapor phase chemical precursors that react with the substrate material sequentially one at a time, slowly forming the thin film. Because of the sequential nature of ALD, the process is self-limiting and offers exceptional control of thin film thicknesses, film composition, and high conformity on high aspect ratio features, such as trenches and sidewalls, making ALD an extremely useful process for the fabrication of semiconductor devices. The purpose of this project was to develop processes and refine process parameters for thin film deposition using an industry grade ALD machine. Thin films were deposited onto silicon substrates with etched features. The films were then examined and characterized using ellipsometry and sidewall conformity was measured using a scanning electron microscope.  This data was used to refine processes and parameters that were then employed by research staff and industry users in the fabrication of semicondctor devices.  Overall, this data can be employed by the semiconductor industry to better understand this process and utilize it to manufactor silicon devies with  greater uniformity and efficiency.

Isolation of silicon (Si) is a microfabrication technique used to isolate selected areas of silicon from interacting with each other using silicon dioxide (SiO2). This processes is done to separate metal oxide semiconductor (MOS) transistors from each other. MOS is a specific way of fabricating devices that is low cost and easy to integrate. It is a very important step in creating integrated circuits. Circuits must be isolated from each other to perform correctly. The smaller the space to separate the circuits, the more circuits can be placed on a device or the smaller the device can be. There are currently two different techniques for isolating silicon. Local Oxidation of Silicon (LOCOS) is the more widely used technique versus the more modern attempt, Shallow Trench Isolation (STI) that is becoming more popular this decade but has many more process steps. Each technique has its pros and cons. LOCOS is a method in which a thin layer of SiO2 is deposited on a wafer, pad oxide, and then a layer of silicon nitride (SiN) is also then deposited as an etch barrier for later stages.Through photolithography processes, including photoresist application, aligning and exposure, a pattern is transferred onto the wafer. The wafer is then put through a plasma etcher to create space for more oxide. Next is for the thermal oxide to be grown, creating an unfortunate “birds beak” that limits feature size of the circuit . The final step is the removal of the remaining nitride and only oxide is left. I am creating a completely new process flow along with a new wafer mask for photolithography to cater to the labs existing equipment, varying different variables and attempting to optimize the technique for the lab. In doing so I will be our lab’s capabilities are tested to see how efficient it is to run the process in the facility and how accurate the results are. The results will be used to determine if in the future certain design features will be able to be implemented in and then fabricated in the lab. Also the question of the techniques viability is answered, if it is still usable and in tolerance with different standards.